Test Process Analysis Tool
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Test Process Analysis Tool TEPROC
User guide

 Product Data Input
 Defect Coverage
 Process Analysis
 Repair loop

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Teproc tool can be used to make a rough analysis of production test efficiency without final details of the product and test applications. Tool makes analysis over whole test process. The method is based on estimating number of defects you will have on your boards. When you have also estimate of defect coverage you can calculate how many defects are found and how many defects are not detected in each test operation and over the process.
This tool is not replacing more accurate tools and analysis methods, which can utilize detailed quality information and product documents (BOM, circuit diagrams, lay-out, etc.).

Estimating number of defects is done in very simple way. When you have understanding of average quality levels of production and complexity of your product, you can estimate number of defect on the coming board. The basic idea is same than in well known diagram (see right) describing how yield is depending on number of components and ppm-level of the production line. This is good presentation e.g. when you want to make people understand that yield will drop when you increase amount of components. It is anyway a bit too straightforward approach for estimating defects in real cases.

In Teproc tool defects are divided to three main groups: termination defects, placement defects and component defects. When also defect coverage of each technology is estimated for these three categories we have good possibility to have rather good estimate of test process efficiency. This categorization is based on standard IPC-7912A: End-Item DPMO for Printed Circuit Board Assemblies. This standard is using also defect group Assembly defects, but that group is not included in this tool (assembly defects group includes defects in areas of cleanness and coating).

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